1. Field of the Invention
The present disclosure relates to a semiconductor device.
2. Description of the Related Art
The semiconductor device is provided by singulating and packaging a semiconductor wafer, on which semiconductor elements are formed through processes such as diffusing and wiring, to be connected to an external circuit. A great number of such semiconductor devices are mounted in an electronic device.
In the semiconductor device, a structure in which a major current path is formed between an upper surface and a lower surface of the semiconductor element is used in the semiconductor element such as a metal oxide semiconductor field effect transistor (MOSFET) using a large current, a bipolar transistor, and a diode. The semiconductor device including the above semiconductor element is difficult to miniaturize after the device has been packaged. This is because an electric connection is made from each of the upper surface and the lower surface of the semiconductor element through die bonding and wire bonding, and the packaging needs to be a plastic type or ceramic type.
Meanwhile, Unexamined Japanese Patent Publication No. 2010-129749 discloses a wafer level chip size package (CSP) technique in which an electric connection is ensured by forming a penetration electrode and rewiring, during an assembly process on a wafer. CSP technique has received attention.
Furthermore, a rewiring technique disclosed in Unexamined Japanese Patent Publication No. 2009-224641 is an effective technique for miniaturizing the device. Thus, by a technique to form a side surface electrode as disclosed in the Unexamined Japanese Patent Publication No. 2009-224641, characteristics of the semiconductor element can be improved and an integration degree thereof can be improved due to a more cubical wiring structure.